Low Transition Test Pattern Generator Architecture for Mixed Mode Built-in-self-test (bist)

In Built-In Self-Test (BIST), test patterns are generated and applied to the circuit-under-test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers (LFSR). Conventional LFSRs normally requires more number of test patterns for testing the architectures which need long test time. Approach: This paper presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with Bipartite (half fixed), Bit-Insertion (either 0 or 1) and its output bits positions are interchanged by swapping techniques (Bit-Swapping). This method introduces Intermediate patterns in between consecutive test vectors generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. LT-GLFSR, are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and improve the correlation between consecutive patterns. LTGLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Discussions: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces power consumption during test for ISCAS’89 bench mark circuits. Generally LT-GLFSR is called GLFSR with Bipartite Technique. Proposed technique is called as LT-GLFSR with BI and BS.